SOI Technology - An Overview
SOI stands for Silicon on Insulator. I remember one time, while working for a fab, I tried to get a customer to investigate SOI for their chip design. Immediately, as if I had given him a mild heart attack, he said “That’s going to be way too expensive.” While he turned out to be right for that application, there are times where it makes perfect sense to pay the cost of SOI. In fact, it can be cheaper than bulk silicon depending on how the chip is designed. It echoed another quote I once heard from another customer that I once spoke to. “The truth is” he said, “No one wants expensive semiconductors.”
Of course, some things are worth the price. SOI technology is used today in many high volume applications. It’s guaranteed that at least one consumer product you used today, car, fridge, smartwatch, etc. contains at least one ASIC built on SOI technology. It’s two main flavors, Partially depleted (PD), and Fully depleted (FD) are highly used in power electronics in automotive, high frequency RF circuits, and low leakage processors for portable and wearable devices.
This post is a high level, full stack explanation of SOI technology beginning at the technology’s conception through technical overview, application spaces, foundry landscape, and current market conditions.
There are two main flavors of SOI technology. Partially depleted (PD), and Fully depleted (FD) SOI. PDSOI Figure 1.b is actually fairly similar to traditional bulk processes. The main point about PDSOI is that when the device is turned on and there’s a channel where electrons flow from source to drain, the inversion layer does not fully reach down to the buried oxide. Compared to bulk processes, it still has the benefits of lower parasitic capacitances, and hence can generally work at faster speeds. There are many different device architectures in PDSOI. I’ve seen device architectures where the drain and source do not contact directly down to the BOX as shown in Fig 1(b), but rather leave space between.
Figure 1 Cross Section views of generic (a) Bulk Transistor (b) PDSOI transistor (c) FDSOI transistor. Source [1]
The technology, shockingly, originated out of IBM and MIT in the 1970s. The original purpose, and still a commonly used application, is to use it for radiation hardened circuits. Unlike bulk silicon, the buried oxide below the device layer can act as a sort of barrier between the transistor itself and incident radiation. What’s interesting is that it took nearly twenty years for the technology to exit the lab and enter production. Growing the Buried Oxide layer was difficult at first. took innovations like SmartCut technology by SOITech to get buried oxide (BOX) and top layer silicon production to a point where substrates were good enough to begin. The first commercial products were PCs that used the lowered parasitic capacitance of the transistors to operate faster. Processors at the time had been approaching speed limitations, and SOI architecture helped reduce the delay at the logic gate level. SOI technology is a prime example of an innovation with ground work that had ben layed for several decades, but only emerged once the market demanded it.
In FDSOI the body terminal is extremely thin, and is fully converted into channel when turned on. This design eliminates the traditional “body”of the device and replaces more with something like a channel which is either on or off. The body can sometimes be a nuisance when designing circuits. Latchup and threshold voltage shifts being main culprits. While this sounds like small technical details to a more business focused audience, but it drastically changes the benefits these devices have and the applications that they service. Because FDSOI has such a thin body, it doesn’t lend itself well to power transistor design. You want a large channel to minimize resistance in high power applications. Rds(on) is a measure of resistance in the transistor when it is turned on, and is often the key determining factor when selecting a process for high voltage applications. PD-SOI technology allows for many fancy high voltage devices with exceptionally low Rds(on) to be built, and these are actively marketed by many foundries.
The largest commercial player in FDSOI technology is Global Foundries. GF’s 22nm and 12nm (22FDX and 12FDX) platforms are workhorses in the industry for these applications. 12nm platform is really as small as you can get in feature size without requiring EUV for lithography, so 12FDX is seen as a way to push performance outside of minimum feature size without incuring the even higher cost of finfet architecture. The 22nm platform has also remained popular for the past 5+ years in power sensitive applications in automotive and mobile, while the 12nm platform goes more aggressively after applications demanding performance from 10nm finfet but requiring exceptionally low power budgets. This makes it a popular platform for applications that demand high density digital but are still extremely cost sensitive.
Many of the other big name foundries offer SOI processes. TSMC, Tower Semi, DB HiTek, and X-FAB are all pure play foundries offering SOI technologies. A few IDMs like ST Micro and NXP have also been reported to use SOI in their products though it is unclear if these are in house or outsourced processes for their products. This is a prime example of where the battles are at the lagging edge. Many foundries competing with each other to get to the best product at the lowest possible price. While there is an idea that semis are winner take all markets, and in some cases they are, the lagging edge is an example of a vibrant market landscape with many players offering unique options. Most SOI processes at commercial foundries are at nodes between 45nm and 180nm, while GF’s 22nm and 12nm platforms have successfully carved out the markets requiring high performance.
Cost/Benefit:
This is an extremely hard thing to do without knowing all details of the processes. Even if I had all the processes’ datashseets in front of me, I could not share them for legal reasons. I can give an overview at a high level of some things that can be kept in mind when performing cost/benefit analysis of SOI vs bulk silicon and comment briefly about certain foundry offerings that are disclosed in the public domain.
The bulk of the added cost in SOI wafers is in the added substrate cost. Meaning the wafers with buried oxide and EPI are more expensive than traditional silicon wafers. The fact that each wafer costs an extra 15%-25% for the foundry to acquire adds consistent cost to each wafer being fabbed out in an SOI process. The real question often comes down to, (1) is the performance superior enough to push the added cost to the customer or (2) can we get the die size small enough to justify the cost of each wafer being 15-25% more expensive? Actually, the latter question is much more about how many more good dies can you get per wafer. If yield goes up, and die size goes down, the added costs of SOI are offset, and you’re left with circuits that perform better than bulk silicon, with a lower production cost per unit than competitors using bulk technologies.
While on the topic of known good dies (NGD), there’s another technical benefit to SOI technology that is under recognized, and directly relates to nuances of the cost benefit analysis. The channel region in an SOI transistor often uses undoped silicon (or epitaxial layer [EPI]). Why is this important with respect to cost? One of the main reasons that dies are thrown out is due to process variation. Specifically, process variations that occur differently on different devices on the chip (mismatch). Anyone who’s designed an analog circuit should be familiar with mismatch, but it is essentially the difference between how two identical devices see process variation. For this reason, two components, like transistors, are typically designed such that they skew in similar directions, making performance based on the ratio of two devices, such that a skew for both devices is mute if both are in the same way. Foundries often specify device parameters with +/- 6 sigma distribution limits. Typically, designers focus on making a robust design close to the mean. Without doping in the channel, as is the case by the nature of bulk silicon (p-type substrate, or n-channel for PMOS device), the effects of process variation are mute for this part of the device. This means that each device in an SOI process can be expected to have less process variation and mismatch between critical circuit elements. This can easily lead to an increase in yield, helping offset the cost of SOI technology.
Another way to get the die size down is of course, if the transistors themselves are smaller. For digital circuits, this doesn’t happen without more expensive lithography tools. For high voltage devices, this is a different story. How a high voltage device is designed to handle large electric fields is dependent on many process details besides channel length. Certain kinds of circuits require large arrays of high voltage devices that take up immense area. It is often the case that the isolation techniques in PD-SOI for high power applications result in lower area consumption compared to bulk HV counterparts, further helping to reduce die cost.
SOI processes also tend to require more masks than bulk processes, adding to both production and NRE expenses. The cost of masks might not be so relevant here for sufficiently high volume, but often affects production costs and total lead times if more processing layers are needed. This is very foundry specific though.
Of course, I have been an advocate here for SOI processes, but in the end, if the application doesn’t demand it, then bulk is still more cost efficient. If the design uses only a few high voltage devices, with low precision on matching analog components, is not highly susceptible to latch up, and generally requires lower performance, then yes, bulk processes still make the most sense. The goal here is to convey that the question of SOI or not SOI is much more nuanced than the added wafer cost, and it can often be a more economical decision even if it isn’t obvious at first.
Citations & Footnotes:
[1] Olejarz, Piotr & Park, Kyoungchul & Macnaughton, Samuel & Dokmeci, Mehmet & Sonkusale, Sameer. (2012). 0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process. Journal of Low Power Electronics and Applications. 2. 155-167. 10.3390/jlpea2020155.
